Various types of Charge-Trap (CT)-based memory devices, such as Silicon-Oxide-Nitride-Oxide-Silicon (SONOS)-based non-volatile memory (NVM) devices, are known in the art. For example, U.S. Pat. No. 8,395,942, whose disclosure is incorporated herein by reference, describes a method to form a plurality of charge storage regions over a tunneling dielectric layer and undercutting a channel using the plurality of charge storage regions as a mask.
U.S. Pat. No. 6,151,249, whose disclosure is incorporated herein by reference, describes NAND-type EEPROM having bit lines and source lines commonly coupled through enhancement and depletion transistors. U.S. Patent Application Publication 2010/0252877, whose disclosure is incorporated herein by reference, describes a non-volatile memory device, which comprises a word line disposed on a substrate, an active region crossing over the word line, and a charge trap layer that is between the word line and the active region.
U.S. Pat. No. 5,768,192, whose disclosure is incorporated herein by reference, describes a non-volatile semiconductor memory cell utilizing asymmetrical charge trapping. The patent describes programming and reading a programmable read only memory (PROM) having a trapping dielectric sandwiched between two silicon dioxide layers that greatly reduces the programming time of conventional PROM devices.
U.S. Pat. No. 8,068,370, whose disclosure is incorporated herein by reference, describes a charge trapping floating gate with asymmetric tunneling barriers. U.S. Pat. No. 7,209,386, whose disclosure is incorporated herein by reference, describes a multiple-gate memory cell, which comprises a semiconductor body and a plurality of gates arranged in series on the semiconductor body. A charge storage structure on the semiconductor body includes charge trapping locations beneath gates in the plurality of gates.